Regviz

Espressif Systems /ESP32-S2 /RTC_CNTL /SWD_CONF

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SWD_CONF

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S2/RTC_CNTL/SWD_CONF#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SWD_RESET_FLAG)SWD_RESET_FLAG 0 (SWD_FEED_INT)SWD_FEED_INT 0SWD_SIGNAL_WIDTH0 (SWD_RST_FLAG_CLR)SWD_RST_FLAG_CLR 0 (SWD_FEED)SWD_FEED 0 (SWD_DISABLE)SWD_DISABLE 0 (SWD_AUTO_FEED_EN)SWD_AUTO_FEED_EN

Description

Super watchdog configuration register

Fields

SWD_RESET_FLAG

Indicates the super watchdog reset flag.
SWD_FEED_INT

Receiving this interrupt leads to feeding the super watchdog via SW.
SWD_SIGNAL_WIDTH

Adjusts the signal width sent to the super watchdog.
SWD_RST_FLAG_CLR

Set to reset the super watchdog reset flag.
SWD_FEED

Set to feed the super watchdog via SW.
SWD_DISABLE

Set this bit to disable super watchdog.
SWD_AUTO_FEED_EN

Set this bit to enable automatic watchdog feeding upon interrupts.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/espressif/svd